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january 2010 doc id 15400 rev 2 1/39 1 stcd22x0, stcd23x0, stcd24x0 multichannel clock distribution circuit features 2, 3 or 4 output buffered clock distribution single-ended square wave (or sine wave) clock input rail-to-rail (0 v to vtcx o) square wave output individual enable pin for each output 1.8 v, high psrr ldo for external clock source voltage supply (vtcxo) no ac coupling capacitor needed ultra-low phase noise and standby current common system clock request, open drain, active low clock enable signal polarities factory programmable (stcd23x0) option pins allow clock enable polarities to be user configurable (stcd22x0 and stcd24x0) high isolation output - to - output & output - to - input 2.5 v to 5.1 v battery supply voltage 40 pf max load driv ing capability per output available in chip scale package (csp) operating temperature : ?20 c to 85 c applications multimode rf clock reference baseband peripheral device clock reference mobile internet devices (mids) flip chip (12-bump, 16-bump) table 1. device summary reference part number channels enable polarity package stcd22x0 stcd2200 (1) 2-channel user program flip chip 12-bump (1.2 mm x 1.6 mm) stcd24x0 stcd2400 4-channel flip chip 16-bump (1.6 mm x 1.6 mm) stcd2410 (1) stcd23x0 stcd2300 (1) 3-channel factory program flip chip 12-bump (1.2 mm x 1.6 mm) stcd2310 (1) stcd2320 (1) stcd2330 (1) 1. contact local st sales office for availability. www.st.com
contents stcd22x0, stcd23x0, stcd24x0 2/39 doc id 15400 rev 2 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2 enable polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 ldo input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2 ldo output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.3 ldo byp pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.4 mc req pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.5 phase noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.6 jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.7 output trace line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.8 typical application connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
stcd22x0, stcd23x0, stcd24x0 list of tables doc id 15400 rev 2 3/39 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin functions (stcd22x0, 2-channel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3. pin functions (stcd23x0, 3-channel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4. pin functions (stcd24x0, 4-channel) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 5. truth table for clock enable (en1-4), master clock request (mc req ) and vtcxo . . . . . . 12 table 6. truth table for enable signals (en1-4), master clock input (mclk) and output clocks (clk1-4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 7. stcd22x0, stcd23x0 and stcd24x0 and enable polarity options . . . . . . . . . . . . . . . . . 13 table 8. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 9. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 10. dc and ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 11. flip chip 12-bump, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 12. flip chip 16-bump, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 13. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 14. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
list of figures stcd22x0, stcd23x0, stcd24x0 4/39 doc id 15400 rev 2 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. hardware hookup (master clock enable active low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4. hardware hookup (master clock enable active high) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 5. connections diagram flip chip 12-bump (stcd22x0, 2-channel). . . . . . . . . . . . . . . . . . . . 8 figure 6. connections diagram flip chip 12-bump (stcd23x0, 3-channel). . . . . . . . . . . . . . . . . . . . 9 figure 7. connections diagram flip chip 16-bump (stcd24x0, 4-channel). . . . . . . . . . . . . . . . . . . . 9 figure 8. jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 9. typical application circuit using stcd 24x0 for rf ends of td-scdma/gsm dual-mode mobile phone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 10. typical application circuit using stcd24x 0 for baseband peripherals in mobile phone. . . 18 figure 11. quiescent current vs. supply voltage (en1 = en2 = en3 = en4 = 1, no master clock input). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 12. quiescent current vs. temperature (en1 = en2 = en3 = en4 = 1, c load = 20 pf, no master clock input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 13. active current vs. temperature (en1 = en2 = en3 = en4 = 1, c load = 20 pf, v cc = 3.8 v, f mclk = 26 mhz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 14. standby current vs. supply voltage (en1 = en2 = en3 = en4 = 0, no master clock input) 20 figure 15. active current vs. supply voltage (en1 = en2 = en3 = en4 = 1, f mclk = 26 mhz, c load = 20 pf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 16. active current vs. master clock input voltage level (en1 = en2 = en3 = en4 = 1, f mclk = 26 mhz, c load = 20 pf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 17. active current vs. master clock frequ ency (en1 = en2 = en3 = en4 = 1, c load = 20 pf) . 21 figure 18. stcd2400 recovery time from standby to active (vtcxo is on) . . . . . . . . . . . . . . . . . . . . 22 figure 19. stcd2400 recovery time from off to on (vtcxo first in standby) . . . . . . . . . . . . . . . . . . . 22 figure 20. output clock rise/fall time (c load = 40 pf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 21. stcd2400 power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 figure 22. stcd2400 power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 23. phase noise input (from the clock source, 26 mhz square wave xo kc2520c26 from kyocera) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 24. phase noise output (include the clock source and stcd2400 additive phase noise) . . . . 26 figure 25. flip chip 12-bump, package mechanical outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 26. flip chip 16-bump, package mechanical outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 27. flip chip 12-bump tape and reel specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 28. flip chip 16-bump tape and reel specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
stcd22x0, stcd23x0, stcd24x0 description doc id 15400 rev 2 5/39 1 description the stcd22x0, stcd23x0 and stcd24x0 are 2, 3 or 4 output clock distribution circuits which accept external square wave or sine wave signals and output rail-to-rail (0 v to vtcxo) square wave signals. they are used to provide a common frequency clock to multimode mobile rf applications. they can also be used for those baseband peripheral applications in mobile phones such as wl an, bluetooth, gps and dvb-h as the clock reference. the stcd22x0, stcd23x0 and stcd24x0 isolate each device driven by their clock outputs and minimize interference between the devices. each of the clock buffers can be disabled to lower the power consumption whenever the connected device does not need the clock. the stcd22x0, stcd23x0 and stcd24x0 accept commonly used mobile master clock frequencies ranging from 10 mhz to 52 mhz. the stcd22x0, stcd23x0 and stcd24x0 have a common clock request (open drain output, active low) controlling the external clock source. a 1.8 v, high psrr ldo is also integrated in the stcd22x0, stcd23x0 and stcd24x0 to supply power to the external clock source (for example, tcxo). stmicroelectronics offers different versions for the enable polarities. the stcd22x0, stcd23x0 and stcd24x0 are available in, respectively, 1.2 mm x 1.6 mm (12-bump), 1.2 mm x 1.6 mm (12-bump) and 1.6 mm x 1.6 mm (16-bump) chip scale packages and can be operated with a battery supply voltage ranging from 2.5 v to 5.1 v. the operating temperature is ?20 to +85 c.
device overview stcd22x0, stcd23x0, stcd24x0 6/39 doc id 15400 rev 2 2 device overview figure 1. logic diagram 1. en3, clk3, en4, and clk4 do not exist for stcd22x0. 2. opt1, opt2, en4, and clk4 do not exist for stcd23x0. v cc mc req vtcxo mclk en1 en2 gnd byp clk1 clk2 clock distribution en3 (1) clk3 (1) clk4 (1)(2) stcd24x0 opt1 (2) en4 (1)(2) opt2 (2) ai14020
stcd22x0, stcd23x0, stcd24x0 device overview doc id 15400 rev 2 7/39 figure 2. block diagram note: enable signals (en1-4) can be factory programmed either active high or active low for stcd23x0 and can have different polarity options by configuring opt1 and opt2 for stcd22x0 and stcd24x0. master clock request (mc req ) is open drain output and active low. figure 3. hardware hookup (master clock enable active low) v cc mc req vtcxo mclk en1 en2 gnd byp clk1 clk2 en3 clk3 en4 clk4 stcd24x0 vtcxo vtcxo vtcxo vtcxo ldo bandgap v cc 1 2 3 4 opt2 opt1 ai14021 c c c clock #4 output clock #3 output clock #2 output clock #1 output enable control en4 en3 en2 en1 clk4 clk3 clk2 clk1 opt1 opt2 mclk mc req vtcxo byp v cc v cc xo en vio stcd24x0 v dd ai14028a
device overview stcd22x0, stcd23x0, stcd24x0 8/39 doc id 15400 rev 2 figure 4. hardware hookup (master clock enable active high) figure 5. connections diagram flip chip 12-bump (stcd22x0, 2-channel) note: opt1 is used to configure en1 polarity. connect opt1 to v cc to configure en1 active high or connect opt1 to gnd to configure en1 acti ve low. in the same way opt2 is used to configure en2. c c c clock #4 output clock #3 output clock #2 output clock #1 output enable control en4 en3 en2 en1 clk4 clk3 clk2 clk1 opt1 opt2 mclk mc req vtcxo byp v cc v cc xo en stcd24x0 v dd ai14028b top view c b a 3 2 1 bottom view clk1 en1 en2 clk2 byp gnd v cc mc req vtcxo mclk opt2 opt1 gnd byp mc req opt1 clk2 v cc vtcxo mclk opt2 en2 en1 clk1 3 2 1 db c da ai14017
stcd22x0, stcd23x0, stcd24x0 device overview doc id 15400 rev 2 9/39 figure 6. connections diagram flip chip 12-bump (stcd23x0, 3-channel) note: en1~en3 can be active high or active low. stmicroelectro nics offers several polarity options, refer to section 3.2: enable polarity for detailed information. figure 7. connections diagram flip chip 16-bump (stcd24x0, 4-channel) note: opt1 is used to configure en1 and en2 polarity. connect opt1 to v cc to configure en1 and en2 active high or connect opt1 to gnd to configure en1 and en2 active low. in the same way opt2 is used to configure en3 and en4. stmicroelectronics offers different control options, refer to section 3.2: enable polarity for detailed information. top view bottom view clk1 en1 en2 clk2 byp gnd v cc mc req vtcxo mclk en3 clk3 gnd byp mc req clk3 clk2 v cc vtcxo mclk en3 en2 en1 clk1 c b a 3 2 1 3 2 1 db c da ai14018 4 3 2 ab cd clk2 en2 en3 clk3 clk1 en1 byp opt1 clk4 1 v cc vtcxo mclk opt2 4 3 2 dc b a clk3 en3 en2 clk2 byp gnd clk1 1 v cc vtcxo mclk bottom view top view en4 mc req opt2 opt1 gnd mc req en1 en4 clk4 ai14019
device overview stcd22x0, stcd23x0, stcd24x0 10/39 doc id 15400 rev 2 table 2. pin functions (stcd22x0, 2-channel) pin number pin name description a1 v cc supply voltage (decouple with a 1 f capacitor to gnd) b1 vtcxo ldo output for external clock source (decouple with a 1 f capacitor to gnd) c1 mclk master clock input d1 opt2 optional pin 2. connect to v cc or gnd on pc board to field configure en2 active high/low. refer to section 3.2: enable polarity for detailed information. a2 byp bypass capacitor input pin (10 nf capacitor should be connected to gnd in order to improve thermal noise performance) b2 gnd supply ground c2 mc req master clock request signal (open drain, active low) d2 opt1 optional pin 1. connect to v cc or gnd on pc board to field configure en1 active high/low. refer to section 3.2: enable polarity for detailed information. a3 clk1 clock output channel - output 1 b3 en1 clock output channel enable-1 (active high/low opt1 field programmable) c3 en2 clock output channel enable-2 (active high/low opt2 field programmable) d3 clk2 clock output channel - output 2 table 3. pin functions (stcd23x0, 3-channel) pin number pin name description a1 v cc supply voltage (decouple with a 1 f capacitor to gnd) b1 vtcxo ldo output for external clock sour ce (decouple with a 1 f capacitor to gnd) c1 mclk master clock input d1 en3 clock output channel enable-3 (active high/low factory laser programmable) a2 byp bypass capacitor input pin (10 nf capa citor should be connected to gnd in order to improve thermal noise performance) b2 gnd supply ground c2 mc req master clock request signal (open drain, active low) d2 clk3 clock output channel - output 3 a3 clk1 clock output channel - output 1 b3 en1 clock output channel enable-1 (active high/low factory laser programmable) c3 en2 clock output channel enable-2 (active high/low factory laser programmable) d3 clk2 clock output channel - output 2
stcd22x0, stcd23x0, stcd24x0 device overview doc id 15400 rev 2 11/39 table 4. pin functions (stcd24x0, 4-channel) pin number pin name description a1 v cc supply voltage (decouple with a 1 f capacitor to gnd) b1 vtcxo ldo output for external clock sour ce (decouple with a 1 f capacitor to gnd) c1 mclk master clock input d1 opt2 optional pin 2. connect to v cc or gnd on pc board to field configure en3 and en4 active high/low. refer to section 3.2: enable polarity for detailed information. a2 byp bypass capacitor input pin (10 nf capa citor should be connected to gnd in order to improve thermal noise performance) b2 gnd supply ground c2 mc req master clock request signal (open drain, active low) d2 opt1 optional pin 1. connect to v cc or gnd on pc board to field configure en1 and en2 active high/low. refer to section 3.2: enable polarity for detailed information. a3 clk1 clock output channel - output 1 b3 en1 clock output channel enable-1 (active high/low opt1 field programmable) c3 en4 clock output channel enable-4 (active high/low opt2 field programmable) d3 clk4 clock output channel - output 4 a4 clk2 clock output channel - output 2 b4 en2 clock output channel enable-2 (active high/low opt1 field programmable) c4 en3 clock output channel enable-3 (active high/low opt2 field programmable) d4 clk3 clock output channel - output 3
device operation stcd22x0, stcd23x0, stcd24x0 12/39 doc id 15400 rev 2 3 device operation 3.1 operation the stcd22x0, stcd23x0 and stcd24x0 are 2, 3 or 4 buffered clock distribution circuits. they accept the clock (either square wave or sine wave) input from an external clock source and send 2, 3 or 4 buffered rail-to-rail (0 v to vtcxo) square wave outputs to different devices. a 1.8 v, high psrr ldo (vtcxo) is also integrated in the stcd22x0, stcd23x0 and stcd24x0 which can be used as a voltage supply for the external master clock source (such as a tcxo). this ldo stops the current increase through pmos when the load current reaches the limit value of the current-limit protection circuit. when the load current falls below the limit values, the current limit is released. each of the stcd22x0, stcd23x0 and stcd24x0 clock outputs can be enabled individually. if the device connected to the output is in standby, and does not require a clock, the buffered output can be disabled to save power consumption. once the buffered output is disabled, it is pulled down to gnd internally. if all the devices connected are in standby, the stcd22x0, stcd23x0 and stcd24x0 are also put into standby mode (the internal ldo is also shut down) for further power consumption savings. all of the output enable signals are logic ored with an open drain output (mc req ) to control the output of the source clock. if the output clock is required by at least one device, the ldo wakes up and the mc req activates the clock source. the truth table for enable signals, the master clock request signal and the vtcxo is given in table 5 . the truth table for enable signals, output clock signals and the master clock is given in table 6 . the stcd22x0, stcd23x0 and stcd24x0 have the master clock input detector integrated. if the input master clock peak-to-peak voltage is below the minimum specified level, even if the outputs are enabled, there are no clock outputs and stcd22x0, stcd23x0 and stcd24x0 enter standby mode. once the master clock peak-to-peak voltage level reaches the minimum value, the output clocks are asserted if the enable pins are active. in table 5 and 6 , the enable signals are active high and the mc req is active low. these enable signals can be active high or active low. the enable polarity is described in section 3.2: enable polarity . customers can select different polarity options for different applications. contact the stmicroelectroni cs local sales office for availability. note: "0" means logic low which disables the cloc k output and "1" means logic high which enables the clock output. this is an active high truth table. refer to section 3.2: enable polarity for the detailed enable active high/low options. table 5. truth table for clock enable (en1-4), master clock request (mc req ) and vtcxo en1 en2 en3 en4 mc req vtcxo 00001gnd 1 0 0 0 0 1.8 v 1 1 0 0 0 1.8 v - -- - 01.8 v 1 1 1 1 0 1.8 v
stcd22x0, stcd23x0, stcd24x0 device operation doc id 15400 rev 2 13/39 note: "0" means logic low and "1" means logic high. when there is no clock output, the clkx pin stays at logic low. "x" means don't care. th is is an active high truth table. refer to section 3.2: enable polarity for the detailed enable active high/low options. 3.2 enable polarity in different applications, the user may have different requirements for enable active high or active low (enable polarities). mc req is active low. stmicroelectronics offers different solutions for the user to obtain different enable polarities. in the stcd22x0 and stcd24x0, the user can configure the enable active high or active low on the pc board by connecting opt1 and opt2 to either v cc or ground. refer to table 7 for detailed information. in the stcd23x0, stmicroelectronics offers 4 enable polarity options by factory programming for the user. refer to table 7 for detailed information. the user should note that opt1 and opt2 must be connected to either v cc or gnd on the pc board and floating on these pins could cause problems. table 6. truth table for enable signals (e n1-4), master clock input (mclk) and output clocks (clk1-4) en1 en2 en3 en4 mclk clk1 clk2 clk3 clk4 0 0 0 0 x no clock no clock no clock no clock 1 0 0 0 clock clock no clock no clock no clock 1 1 0 0 clock clock clock no clock no clock --------- 1 1 1 1 clock clock clock clock clock table 7. stcd22x0, stcd23x0 and stcd24x0 and enable polarity options part number enable pola rities (opt1, opt2) enable polarity program method stcd2200 opt1 connected to v cc , en1 active high opt1 connected to gnd, en1 active low opt2 controls en2 user program stcd2400 opt1 connected to v cc , en1 and en2 active high opt1 connected to gnd, en1 and en2 active low opt2 controls en3 and en4 stcd2410 opt1 connected to v cc , en1 active high opt1 connected to gnd, en1 active low opt2 controls en2, en3, and en4 stcd2300 en1, en2 and en3 all active low factory program stcd2310 en1, en2 active low, and en3 active high stcd2320 en1, en2 active high and en3 active low stcd2330 en1, en2 and en3 all active high
application information stcd22x0, stcd23x0, stcd24x0 14/39 doc id 15400 rev 2 4 application information 4.1 ldo input capacitor a 1 f input capacitor is required for the in put of the ldo of the stcd22x0, stcd23x0 and stcd24x0 (the amount of capacitance can be increased without limit). this capacitor must be located as close as possible to the v cc pin on the pc board and return to a clean analog ground. any good quality ceramic, tantalum or film capacitor can be used for this capacitor. 4.2 ldo output capacitor a 1 f external capacitor is required for the output vtcxo of the ldo of the stcd22x0, stcd23x0 and stcd24x0. the stcd22x0, stcd23x0 and stcd24x0 are designed to work with low esr (equivalent series resistance) ceramic capacitors. make sure the esr is lower than 500 m to stabilize the vtcxo. also, capa citor tolerance and variation with temperature must be considered to assure the minimum amount of capacitance provided at all times. this capacitor should be located as close as possible to the vtcxo pin on the pc board. 4.3 ldo byp pin a 10 nf ceramic capacitor is required for the ldo byp pin to ensure lower noise. any good quality ceramic, tantalum or film capacitor can be used. the capacitor should be located as close as possible to the byp pin on the pc board. 4.4 mc req pin in the stcd22x0, stcd23x0, and stcd24x0, the mc req pin is open drain and active low. since mc req is active low, if none of the clock output is required, the stcd22x0, stcd23x0 and stcd24x0 are set to standby mode which turns off the internal ldo vtcxo. mc req is designed as an open drain structure. a pull-up resistor (50 k recommended) is needed on the pc board to connect this pin to an external 1.8 v supply. make sure the current flowing through this pin is kept within 3 ma to guarantee the proper function of the circuit. if the mc req function is not used in the application, the user can connect this pin to gnd or leave it unconnected. other functions of the stcd2xx0 will not be affected.
stcd22x0, stcd23x0, stcd24x0 application information doc id 15400 rev 2 15/39 4.5 phase noise phase noise is a frequency domain phenomenon and is a critical specification in reference clocks. it is illustrated by a continuous spreading of the energy of the wave mainly caused by random noise. the phase noise is normally specif ied with a unit of dbc/hz at a given offset in frequency (for example, 10 khz) from the carrier wave (for example, 26 mhz). the value of the phase noise is the difference of the power contained within 1 hz bandwidth of the offset frequency to the power at the carrier frequency. the total phase noise of the clock tree is obtained by adding the additive phase noise of stcd22x0, stcd23x0 and stcd24x0 and the phase noise of the clock source (for example, tcxo) in power which is illustrated in equation 1 . equation 1 where: pn t is the total phase noise in dbc/hz pn c is the additive phase noise of stcd22x0, stcd23x0 and stcd24x0 and pn x is the phase noise of clock source make sure the total phase noise is kept within the phase noise requirement of each application pn a . the user should choose the right tcxo with proper phase noise to meet the requirement. a 10 pn 10 pn t pn ) 10 10 log( 10 pn x c < + =
application information stcd22x0, stcd23x0, stcd24x0 16/39 doc id 15400 rev 2 4.6 jitter in the time domain, energy spreading can result in jitter, which is the same phenomenon as phase noise in the frequency domain. as a sine wave passes its zero-crossing or a square wave changes state, the real clock signal transition is not exactly the same as the ideal case, thus causing variation in the waveform transition point. this deviation of the transition point is known as jitter as illustrated in figure 8 . figure 8. jitter in figure 8 the square wave ideal transition point should happen at points 1, 2, 3, 4 and 5, and each "ideal" period pi1 to pi4 should be the same, thus no time jitter has occurred. actually, the real transition point happens at points 6, 7, 8, 9 and 10, thus causing "real" periods pr1 to pr4 to not be the same, and exhibit visible jitter. if each of the real periods of the cycles (pr1 to pr4) is measured, period jit ter is obtained. the cycle-to-cycle jitter is also obtained by calculating the difference between two adjacent periods (for example, pr2- pr1, pr3-pr2 ?). these periods of jitter are described as peak-to- peak jitter and are calculated by subtracting the minimum value from the maximum value or may also be described by the root-mean- square (rms) value, representing one standard deviation of the gaussian distribution. 4.7 output trace line the stcd22x0, stcd23x0 and stcd24x0 is designed with maximum 50 impedance output. on the pc board, a 50 transmission line with proper series termination should be used to avoid signal distortion and reflection. 2345 1 pi1 pi 2 pi 3 pi 4 pr1 pr2 pr3 pr4 t 78910 6 ideal transfer point real square wave transfer point ai14029
stcd22x0, stcd23x0, stcd24x0 application information doc id 15400 rev 2 17/39 4.8 typical appli cation connections the stcd2400 clock distribution circuit requires a source clock input as the reference clock (for example, xo). at most 4 devices can be connected to the outputs. the typical application circuit using stcd2400 is shown in figure 9 and 10 . the mc req is open drain output and active low. a pull-up resistor is needed to connect to an external 1.8 v supply vio. if the clock source enable is active high, the user can use vtcxo as the master clock enable control signal, please refer to figure 4 for the detailed connection. in figure 9 , the clock from xo is distributed to the td-scdma transmitter and receiver and gsm transceiver separately to be used as reference clocks. in figure 10 , the buffer #4 output is fed into the bluetooth system. in order to allow minimum power consumption, a bluetooth system always has a clock request feature. if the bluetooth system does not require the clock, the clock request disables the clock output. the enable pins can also be connected to an external 1.8 v supply to force the buffer to always be on. in figure 9 and 10 , all the output clock enables are active high since both opt1 and opt2 are connected to v cc . figure 9. typical application circuit using stcd24x0 for rf ends of td- scdma/gsm dual-mode mobile phone stcd24x0 v cc mc req vtcxo mclk en1 en2 gnd byp clk1 clk2 en3 clk3 en4 clk4 xo en vio c c c gsm transceiver td-scdma receiver td-scdma transmitter mode selection opt1 opt2 v cc v dd ai14022
application information stcd22x0, stcd23x0, stcd24x0 18/39 doc id 15400 rev 2 figure 10. typical application circuit usi ng stcd24x0 for baseband peripherals in mobile phone bluetooth internal_req stcd24x0 v cc mc req vtcxo mclk en1 en2 gnd byp clk1 clk2 en3 clk3 en4 clk4 xo en vio c c c bt_external_req wlan gps other device opt1 opt2 v cc v dd ai14023
stcd22x0, stcd23x0, stcd24x0 typical operating characteristics doc id 15400 rev 2 19/39 5 typical operating characteristics typical operating characteristics are at t a = 25 c, c load = 20 pf at each channel, v cc = 3.8 v, f mclk = 26 mhz. figure 11. quiescent current vs. supply voltage (en1 = en2 = en3 = en4 = 1, no master clock input) figure 12. quiescent current vs. temperature (en1 = en2 = en3 = en4 = 1, c load = 20 pf, no master clock input) 67 68 69 70 71 72 73 74 75 2. 3 2. 7 3. 1 3. 5 3. 9 4. 3 4. 7 5.1 5. 5 quiescent current i cc (a) supply voltage v cc (v) am00496v1 am00497v1 0 20 40 60 80 100 ?30 ?20 0 25 50 85 quiescent current i cc (a) temperature (c)
typical operating characteristi cs stcd22x0, stcd23x0, stcd24x0 20/39 doc id 15400 rev 2 figure 13. active current vs. temperature (en1 = en2 = en3 = en4 = 1, c load = 20 pf, v cc = 3.8 v, f mclk = 26 mhz) figure 14. standby current vs. supply voltage (en1 = en2 = en3 = en4 = 0, no master clock input) 0 2 4 6 8 ?30 ?20 0 25 50 85 1 channel enabled 2 channels enabled 3 channels enabled 4 channels enabled am00498v1 active current i act (ma) temperature (c) 0 0.05 0.1 0.15 0.2 0.25 2. 3 2. 5 2. 7 2. 9 3 . 1 3 . 3 3 . 5 3 . 7 3 . 9 4. 1 4. 3 4. 5 4. 7 4. 9 5. 1 5. 3 5. 5 su pply volt a ge v cc (v) s t a nd b y c u rrent i s b ( a) am00500v1
stcd22x0, stcd23x0, stcd24x0 typical operating characteristics doc id 15400 rev 2 21/39 figure 15. active current vs. supply voltage (en1 = en2 = en3 = en4 = 1, f mclk = 26 mhz, c load = 20 pf) figure 16. active current vs. master clock inpu t voltage level (en1 = en2 = en3 = en4 = 1, f mclk = 26 mhz, c load = 20 pf) figure 17. active current vs. master clock frequency (en1 = en2 = en3 = en4 = 1, c load = 20 pf) 1 channel enabled 2 channels enabled 3 channels enabled 4 channels enabled am00612v1 active current i act (ma) supply voltage v cc (v) 0 1 2 3 4 5 6 2. 3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 1 channel enabled 2 channels enabled 3 channels enabled 4 channels enabled am00613v1 active current i act (ma) master clock f mclk voltage level (vpp) 0 1 2 3 4 5 6 7 0. 5 0. 8 1. 1 1. 4 1.8 0 5 10 15 m as ter clock fre qu ency f mclk (mhz) active c u rrent i act (ma) 1 ch a nnel en ab led 2 ch a nnel s en ab led 3 ch a nnel s en ab led 4 ch a nnel s en ab led am00614v1 510 40 4550 55 3 5 3 0 25 20 15
typical operating characteristi cs stcd22x0, stcd23x0, stcd24x0 22/39 doc id 15400 rev 2 figure 18. stcd2400 recovery time from standby to active (vtcxo is on) figure 19. stcd2400 recovery time from off to on (vtcxo first in standby)
stcd22x0, stcd23x0, stcd24x0 typical operating characteristics doc id 15400 rev 2 23/39 figure 20. output clock rise/fall time (c load = 40 pf)
typical operating characteristi cs stcd22x0, stcd23x0, stcd24x0 24/39 doc id 15400 rev 2 figure 21. stcd2400 power-up sequence figure 22. stcd2400 power-down sequence
stcd22x0, stcd23x0, stcd24x0 typical operating characteristics doc id 15400 rev 2 25/39 figure 23. phase noise input (from the clock source, 26 mhz square wave xo kc2520c26 from kyocera)
typical operating characteristi cs stcd22x0, stcd23x0, stcd24x0 26/39 doc id 15400 rev 2 figure 24. phase noise output (include the clock source and stcd2400 additive phase noise)
stcd22x0, stcd23x0, stcd24x0 maximum ratings doc id 15400 rev 2 27/39 6 maximum ratings stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not imp lied. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. table 8. absolute maximum ratings symbol parameter value unit t stg storage temperature (v cc off) ?55 to 150 c t sld (1) 1. reflow at peak temperature of 260 c. the time above 255 c must not exceed 30 seconds. lead-free bump solder temperature for 10 seconds 260 c t j maximum junction temperature 150 c v cc supply voltage ?0.3 to 6 v v in input clock voltage ?0.3 to 3.6 v v en voltage on enable pins ?0.3 to 3.6 v v opt optional pins voltage ?0.3 to 6 v mc req master clock request ?0.3 to 3.6 v
dc and ac parameters stcd22x0, stcd23x0, stcd24x0 28/39 doc id 15400 rev 2 7 dc and ac parameters this section summarizes the operating measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristics tables that follow are derived from tests performed under the measurement conditions summarized in table 9 . designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. table 9. operating and ac measurement conditions parameter condition unit v cc supply 2.5 to 5.1 v input source clock voltage (mclk) 0 to 1.8 v output clock voltage (clk1-4) 0 to 1.8 v device enable voltage (en1-4) 0 to 1.8 v source clock request voltage (mc req )0 to 1.8v optional pins voltage (opt1, opt2) 0 to v cc v ambient operating temperature (t a ) ?20 to +85 c flip-chip thermal resistance (r thja )90 c/w table 10. dc and ac characteristics sym. parameter condition (1) min typ max unit vtcxo (low dropout output) v cc supply voltage 2.5 5.1 v v tcxo output voltage i load = 5 ma 1.75 1.8 1.85 v i o maximum output current 20 ma v oacc total output accuracy (2) ?5% 5% i cl current limit protection v tcxo = 0 v 30 90 ma v reg line regulation (3) i load = 20 ma 0.5 10 mv i reg load regulation (3) i load = 10 a to 20 ma 0.4 10 mv i tr load transient (3) i load = 10 a to 20 ma i tr = 1 s 100 110 mv i load = 20 ma to 10 a i tr = 1 s 100 110 mv
stcd22x0, stcd23x0, stcd24x0 dc and ac parameters doc id 15400 rev 2 29/39 psrr power supply rejection ratio (3)(4) v cc = 2.5 v to 5.1 v, f ripple = 217 hz, i load = 20 ma 60 67 db v cc = 2.5 v to 5.1 v, f ripple = 1 khz, i load = 20 ma 40 60 v cc = 2.5 v to 5.1 v, f ripple = 1 mhz, i load = 20 ma 40 v cc = 2.5 v to 5.1 v, f ripple = 3.25 mhz, i load = 20 ma 40 e n output noise voltage (3) i load = 5 ma, 10 hz to 100 khz 45 v rms t st startup time (3) v tcxo > 90%, i load = 10 a to 20 ma 150 400 s t f output voltage falling time (3) v tcxo < 10%, i load = 0 120 400 s clock distribution f mclk master clock (from external clock source) square wave / sine wave 10 26 52 mhz f clk duty cycle 40 50 60 % v in input clock voltage level (5) square wave 0.8 1.8 vtcxo + 0.2 vpp sine wave 0.8 1 vtcxo + 0.2 vpp v oh output high c l = 20 pf vtcxo ? 0.05 vtcxo v v ol output low c l = 20 pf 0.05 v t r/f rise/fall time (6) c l =10 pf~ 40 pf 1 2 5 ns i qc quiescent current (7) (including ldo) 1 channel enabled 80 200 a 2 channels enabled 80 200 3 channels enabled 80 200 4 channels enabled 80 200 i cc active current (8) 1 channel enabled 1.9 ma 2 channels enabled 3.0 3 channels enabled 4.1 4 channels enabled 5.2 i sb standby current (including ldo) all buffers off 0.2 1 a r in input impedance > 100 k table 10. dc and ac characteristics (continued) sym. parameter condition (1) min typ max unit
dc and ac parameters stcd22x0, stcd23x0, stcd24x0 30/39 doc id 15400 rev 2 c in input capacitance 3 4 pf i oo output to output isolation 45 db i oi output to input isolation 45 db v enh enable voltage high (9) for en1-en4 1.2 v v enl enable voltage low (9) for en1-en4 0.6 v v opth opt pins voltage high for opt1 and opt2 v cc ?0.3 v cc v v optl opt pins voltage low for opt1 and opt2 gnd gnd+0.3 v p n additive phase noise (3)(10) at 1 khz offset ?135 dbc/ hz at 10 khz offset ?145 at 100 khz offset ?150 t jp additive period jitter (3) rms value 10 ps t jc additive cycle-cycle jitter (3) rms value 10 ps t recb buffer recovery time from off to on stcd2xx0 active 1 10 s t recc stcd2xx0 recovery time from standby to active (include ldo wakeup time) 500 s t pd input to output propagation delay (3) voltage transfer at 50% 3.5 6 ns c l capacitive load for each channel 20 40 pf r l resistive load for each channel 10 k z out output impedance for each channel 50 1. valid for ambient operating temperature: t a = ?20 c to 85 c; v cc = 2.5 v to 5.1 v; typical t a = 25 c; load capacitance = 20 pf, f mclk = 26 mhz (except where noted). 2. total accuracy includes line and load regulation, temperat ure and process condition. it does not include load and line transients. 3. simulated and determined via design and not 100% tested. 4. ripple voltage = 0.1 vpp. 5. clock input voltage level should not exceed vtcxo voltage. 6. the rise time is measured when clock edge transfe rs from 10% v cc to 90%v cc . the fall time is measured when clock edge transfers from 90%v cc to 10%v cc . the output rise/fall time is guaranteed for all input slew rates. 7. the quiescent current is measured when the enable pins are active, but wi th no input master clock signal (f mclk = 0 hz). 8. the active current depends on the input master clock vpp and frequency and the load condition. the typical test condition is 26 mhz with 1.8 vpp master clock input, c l = 20 pf. 9. the test condition is v enh = 1.8 v and v enl = 0 v. when output enables simultaneously , there is no intentional skew in design between the output clocks. 10. guaranteed for all input clock slew rates. table 10. dc and ac characteristics (continued) sym. parameter condition (1) min typ max unit
stcd22x0, stcd23x0, stcd24x0 package mechanical data doc id 15400 rev 2 31/39 8 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 25. flip chip 12-bump, package mechanical outline 7504892_l(e)
package mechanical data stcd22x0, stcd23x0, stcd24x0 32/39 doc id 15400 rev 2 table 11. flip chip 12-bump, package mechanical data symbol mm in min typ max min typ max a 0.55 0.61 0.66 0.022 0.024 0.026 a1 0.17 0.21 0.24 0.007 0.008 0.009 a2 0.38 0.40 0.42 0.015 0.016 0.017 b 0.22 0.26 0.30 0.008 0.010 0.012 d 1.55 1.60 1.65 0.061 0.063 0.065 d1 1.20 0.047 e 1.15 1.20 1.25 0.045 0.047 0.049 e1 0.80 0.031 e 0.36 0.40 0.44 0.014 0.016 0.017 de 0.18 0.20 0.22 0.007 0.008 0.009 f 0.185 0.195 0.210 0.007 0.008 0.008 ccc 0.05 0.002
stcd22x0, stcd23x0, stcd24x0 package mechanical data doc id 15400 rev 2 33/39 figure 26. flip chip 16-bump, package mechanical outline 7504892_l(a)
package mechanical data stcd22x0, stcd23x0, stcd24x0 34/39 doc id 15400 rev 2 table 12. flip chip 16-bump, package mechanical data symbol mm in min typ max min typ max a 0.55 0.61 0.66 0.022 0.024 0.026 a1 0.17 0.21 0.24 0.007 0.008 0.009 a2 0.38 0.40 0.42 0.015 0.016 0.017 b 0.22 0.26 0.30 0.008 0.010 0.012 d 1.55 1.60 1.65 0.061 0.063 0.065 d1 1.20 0.047 e 1.55 1.60 1.65 0.061 0.063 0.065 e1 1.20 0.047 e 0.36 0.40 0.44 0.014 0.016 0.017 sd 0.18 0.20 0.22 0.007 0.008 0.009 se 0.18 0.20 0.22 0.007 0.008 0.009 f 0.185 0.195 0.210 0.007 0.008 0.008 ccc 0.05 0.002
stcd22x0, stcd23x0, stcd24x0 package mechanical data doc id 15400 rev 2 35/39 figure 27. flip chip 12-bump tape and reel specifications 12 b fc
package mechanical data stcd22x0, stcd23x0, stcd24x0 36/39 doc id 15400 rev 2 figure 28. flip chip 16-bump tape and reel specifications 16 b fc
stcd22x0, stcd23x0, stcd24x0 part numbering doc id 15400 rev 2 37/39 9 part numbering table 13. ordering information scheme for other options, or for more information on any aspect of this device, please contact the st sales office nearest you. example: stcd 22 0 0 f3 5 f device type stcd = clock distribution channels 22 = 2-channel (1) 1. contact local st sales office for availability. 23 = 3-channel (1) 24 = 4-channel enable polarity stcd22x0 (user programmable) 0 = opt1 sets en1, opt2 sets en2 stcd23x0 (factory programmable) 0 = en1 , en2 , en3 1 = en1 , en2 , en3 2 = en1, en2, en3 3 = en1, en2, en3 stcd24x0 (user programmable) 0 = opt1 sets en1 and en2, opt2 sets en3 and en4 1 = opt1 sets en1, opt2 sets en2, en3, and en4 (1) master clock request (mc req ) 0 = mc req active low package f3 = flip chip, lead-free, pitch = 400 m, bump = 250 m (12-bump for 2- or 3-channel, 16-bump for 4-channel) temperature range 5 = ?20 c to +85 c shipping method f = ecopack ? package, tape & reel
revision history stcd22x0, stcd23x0, stcd24x0 38/39 doc id 15400 rev 2 10 revision history table 14. document revision history date revision changes 26-aug-2009 1 initial release. 11-jan-2010 2 updated footnote 5 in table 10: dc and ac characteristics .
stcd22x0, stcd23x0, stcd24x0 doc id 15400 rev 2 39/39 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in military , air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2010 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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